library verilog;
use verilog.vl_types.all;
entity fifo is
    generic(
        B               : integer := 8;
        W               : integer := 4
    );
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        wr              : in     vl_logic;
        rd              : in     vl_logic;
        w_data          : in     vl_logic_vector;
        r_data          : out    vl_logic_vector;
        empty           : out    vl_logic;
        full            : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of B : constant is 1;
    attribute mti_svvh_generic_type of W : constant is 1;
end fifo;
